Buried Capacitance in Printed Circuit Boards
You are cordially invited to a Technical Presentation by the IEEE Huntsville EMC Chapter. Mr. John Andresakis of Oak-Mitsui Technologies, will present “Use Of Buried Capacitance Layers In Printed Circuit Boards: Performance And Lessons From A Real World Example”.
A complimentary supper of “Fried Chicken with All the Fixin’s” will be provided, care of Mr. Mike Kirk, Agilent Technologies.
Abstract
Embedded capacitor technology has been driven by the need to save board area and/or reduce board size, increase functionality, lower costs and improve electrical performance. This technology has been utilized to enhance signal integrity, reduce impedance at high frequency and dampen noise, and not necessarily just to remove discrete capacitors.
We will show that by using thin core planes and simulation tools one can reduce the number of discrete capacitors and get better electrical performance. The actual number and type (size) of capacitors removed will be presented. In addition to discrete capacitor reduction, the amount of electro-magnetic radiation from the board (which can cause EMI issues) will be shown to be reduced by utilizing the embedded capacitor planes. This is attributed to the reduction in power/ground plane resonance. With a good predictive model, the decision to utilize embedded capacitors is simplified.
The meeting will be held at ADTRAN in the East Tower Lobby Conference Room. The meeting is open to anyone interested in EMC. IEEE membership is not required to attend.
Please RSVP to Paul Stover by 11 May 2010 with your intent to attend.
I hope to see you there!
Event Details and Reservations
Date: Thursday, 13 May 2010
Time: 5:30 p.m.
Location: ADTRAN Inc. 2 East Conference Center Room #273
(Do not park in the visitor parking lot or try to use the main entrance to the East Tower.)
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